Architecture of a Quantum Multicomputer Optimized for Shor’s Factoring Algorithm

Quantum computers exist, and offer tantalizing possibilities of dramatic increases in computational power, but scaling them up to solve problems that are classically intractable offers enormous technical challenges. Distributed quantum computation offers a way to surpass the limitations of an individual quantum computer. I propose a quantum multicomputer as a form of distributed quantum computer. The quantum multicomputer consists of a large number of small nodes and a qubus interconnect for creating entangled state between the nodes. The primary metric chosen is the performance of such a system on Shor’s algorithm for factoring large numbers: specifically, the quantum modular exponentiation step that is the computational bottleneck. This dissertation introduces a number of optimizations for the modular exponentiation, including quantum versions of the classical carry-select and conditional-sum adders, improvements in the modular arithmetic, and a means for reducing the amount of expensive, error-prone quantum computation by increasing the amount of cheaper, more reliable classical computation. Parallel implementations of these circuits are evaluated in detail for two abstract architectural models, one (called AC) which supports long-distance communication between quantum bits, or qubits, and one which allows only communication between nearest neighbors in a linear layout (called NTC). My algorithms reduce the latency, or circuit depth, to complete the modular exponentiation of an n-bit number from O(n) to O(n log n) for AC and O(n log n) for NTC. Including improvements in the constant factors, calculations show that these algorithms are one million times and thirteen thousand times faster on AC and NTC, respectively, when factoring a 6,000-bit number. These circuits also reduce the demands on quantum error correction from ∼ 210n to ∼ 12n log2 n for AC and ∼ 3n for NTC, potentially reducing the number of levels of error-correction encoding or allowing execution on more error-prone hardware. Extending to the quantum multicomputer, I calculate the performance of several types of adder circuits for several different hardware configurations. Five different